373 lines
21 KiB
C
373 lines
21 KiB
C
/*****************************************************************************
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* Module : Configs
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* File : config_define.h
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* Function : 定义用户参数常量
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*****************************************************************************/
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#ifndef CONFIG_DEFINE_H
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#define CONFIG_DEFINE_H
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/*****************************************************************************
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* Module : 系统定义
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*****************************************************************************/
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#define XOSC_CLK_HZ 26000000
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/*****************************************************************************
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* Module : 芯片选型
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*****************************************************************************/
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#define CHIP_5681G 0 //QFN40
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#define CHIP_5682C 1 //QFN32
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/*****************************************************************************
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* Module : 显示相关配置选择列表
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*****************************************************************************/
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/* 显示驱动屏选择 */
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#define DISPLAY_NO 0 //无显示模块
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#define DISPLAY_LCD 0x100 //选用LCD点阵屏做为显示驱动
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#define DISPLAY_LCDSEG 0x200 //选用断码屏做为显示驱动
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#define DISPLAY_LEDSEG 0x400 //选用数码管做为显示驱动
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#define DISPLAY_TFT 0x800 //选用彩屏做为显示驱动
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#define GUI_NO DISPLAY_NO //无主题，无显示
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#define GUI_TFT_320_ST77916 (DISPLAY_TFT | 0x01) //彩屏 320 * 385
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#define GUI_TFT_360_GC9C01 (DISPLAY_TFT | 0x02) //彩屏 360 * 360
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#define GUI_OLED_466_ICNA3310B (DISPLAY_TFT | 0x03) //OLED彩屏 466 * 466
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#define GUI_TFT_JD9853 (DISPLAY_TFT | 0x04) //JD9853 240*296 DSPI 屏
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#define GUI_TFT_240_ST7789 (DISPLAY_TFT | 0x05) //ST7789 240*296 SPI 屏
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#define GUI_TFT_240_ST7789W3 (DISPLAY_TFT | 0x06) //ST7789w3 240*296 SPI 屏
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#define GUI_TFT_240_296_GCGD3030 (DISPLAY_TFT | 0x07) //GCGH 240*296 SPI 屏
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#define GUI_TFT_128_160_XSJ3023HSD (DISPLAY_TFT | 0x08) //XSJ 128*160 SPI 屏
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#define GUI_TFT_240_296_JD9853 (DISPLAY_TFT | 0x09) //GCGH 240*296 SPI 屏
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#define GUI_TFT_240_296_JD9853A (DISPLAY_TFT | 0x10) //GCGH 240*296 SPI 屏
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#define GUI_TFT_240_284_XSJ3030 (DISPLAY_TFT | 0x0A) //GCGH 240*284 SPI 屏
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#define GUI_TFT_240_240_NV3002B1N (DISPLAY_TFT | 0x0B) //(中鑫盛)NV3002B 1N 240*240 SPI 屏
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#define GUI_TFT_240_240_GC9307 (DISPLAY_TFT | 0x0C) //GC9307 240*240 SPI 屏
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#define GUI_TFT_240_296_BOE7789P3 (DISPLAY_TFT | 0x0D) //BOE 7789P3 240*296 SPI 屏
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#define GUI_TFT_240_240_ST7789P3 (DISPLAY_TFT | 0x0E) //亚创7789P3+IVO 240*240 SPI 屏
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#define GUI_TFT_240_296_GC9037BOE (DISPLAY_TFT | 0x0F) //星火BOE 9037 240*296 SPI 屏
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/* TP驱动选择 */
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#define CTP_NO 0
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#define CTP_CST8X 0x100
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#define CTP_CHSC6X 0x200
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#define CTP_AXS5106 0x400
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#define CTP_AXS5106L 0x800 /*TB36 V2.0*/
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#define CTP_SPT5113C 0x1000
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/* 爱协生AX5106触摸IC*/
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#define CTP_TZ1_T168_AXS5106L_TJD_V01 (CTP_AXS5106L | 0x01) /*ZX_S2404094_TZ1_T168_AXS5106L_TJD_V01_00_20240402_App*/
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#define CTP_TZ64_T168_AXS5106L_TJD_V01 (CTP_AXS5106L | 0x02) /*ZX_S2404094_TZ1_T168_AXS5106L_TJD_V01_00_20240402_App*/
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#define CTP_TZ1_T83_AXS5106L_TJD_V01 (CTP_AXS5106L | 0x03) /*ZX_S2406077_TZ1_T83_AXS5106L_TJD_V01_00_20240628_App*/
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#define CTP_T14833_TZ64A_KP871_AXS5106L_TJD_V01 (CTP_AXS5106L | 0x04) /*ZX_S2407020_T14833-TZ64A_KP871-S107_AXS5106L_TJD_V01_00_20240709_App*/
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#define CTP_TZ2_TB71_A_AXS5106L_TJD_V01 (CTP_AXS5106L | 0x05) /*ZX_S2407031_TZ2_TB71-A_AXS5106L_TJD_V01_00_20240715_App*/
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#define CTP_T14833_TZ64A_KP871_AXS5106L_TJD_V02 (CTP_AXS5106L | 0x06) /*ZX_S2407020_T14833-TZ64A_KP871-S107_AXS5106L_TJD_V01_02_20240814_App*/
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#define CTP_TZ19A_KYA002_AXS5106L_TJD_V01 (CTP_AXS5106L | 0x07) /*ZX_S2409003_TZ19A_KYA002_AXS5106L_TJD_V01_00_20240902_App*/
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#define CTP_TZ19A_FWT038_AXS5106L_TJD_V01 (CTP_AXS5106L | 0x08)
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#define CTP_TZ19A_FWT038_KYA012_AXS5106L_TJD_V01 (CTP_AXS5106L | 0x09) /*翼东1299，FWT038——ZX_S2411026_TZ19A_FWT030_KYA012_AXS5106L_TJD_V01_00_20241114_App*/
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#define CTP_TZ19A_MWD_1219_V1_AXS5106L_TJD_V01 (CTP_AXS5106L | 0x10) /*ZX_S2410064_TZ19A_MWD-1219-V1_AXS5106L_TJD_V01_00_20241029_App*/
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#define CTP_TZ19A_KYA029_AXS5106L_TJD_V01 (CTP_AXS5106L | 0x0A)
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/* 普林芯驰SPT5113C触摸IC */
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#define CTP_SPT5113C_KYA012V1_FWT_064_V1 (CTP_SPT5113C | 0x01) //"spt5113c_firmware_KYA012V1_FWT-064-V1_241129_01.h"
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#define CTP_SPT5113C_B796A01_FWT030V0 (CTP_SPT5113C | 0x02) /*spt5113c_firmware_B796A01_FWT030V0_241129_01.h*/
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#define CTP_SPT5113C_TZ1_MWD1303_01 (CTP_SPT5113C | 0x03) /*spt5113c_firmware_TZ1_MWD1303_01.h*/
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#define CTP_SPT5113C_TZ1_TB36V2 (CTP_SPT5113C | 0x04) /*spt5113c_firmware_TZ1_TB36V2_2411271634.h*/
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#define CTP_SPT5113C_TZ19A_S693_FWT038 (CTP_SPT5113C | 0x05) /*spt5113c_firmware_TZ19A_2TP_S693+FWT038_01.h*/
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#define CTP_SPT5113C_TZ32A_Q1328 (CTP_SPT5113C | 0x06) /*spt5113c_firmware_tz32a_q1328_01.h*/
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#define CTP_SPT5113C_TZ64A_KB871_V01 (CTP_SPT5113C | 0x07) /*spt5113c_firmware_TZ64A_KB871_01.h*/
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#define CTP_SPT5113C_TZ2_TB71A_01 (CTP_SPT5113C | 0x08) /*spt5113c_firmware_TZ2_TB71A_01.h*/
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#define CTP_SPT5113C_TZ19A_2TP_S693_FWT038_01 (CTP_SPT5113C | 0x09) /*spt5113c_firmware_TZ19A_2TP_S693+FWT038_01.h*/
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#define CTP_SPT5113C_TZ19A_2TP_MWD1219_S782_01 (CTP_SPT5113C | 0x0A) /*spt5113c_firmware_TZ19A_2TP_MWD1219+S782_01.h*/
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/*****************************************************************************
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* Module : FLASH大小定义
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*****************************************************************************/
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#define FSIZE_8M 0x800000
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#define FSIZE_4M 0x400000
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#define FSIZE_2M 0x200000
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#define FSIZE_1M 0x100000
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#define FSIZE_512K 0x80000
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/*****************************************************************************
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* Module : 提示音语言配置选择列表
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*****************************************************************************/
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#define LANG_EN 0 //英文提示音
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#define LANG_ZH 1 //中文提示音
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#define LANG_EN_ZH 2 //英文、中文双语提示音
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/*****************************************************************************
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* Module : ADC通路选择列表
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*****************************************************************************/
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#define ADCCH_PA0 0 //SARADC channel 0
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#define ADCCH_PA1 1 //SARADC channel 1
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#define ADCCH_PB0 2 //SARADC channel 2
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#define ADCCH_PB1 3 //SARADC channel 3
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#define ADCCH_PB2 4 //SARADC channel 4
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#define ADCCH_PB3 5 //SARADC channel 5
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#define ADCCH_PB4 6 //SARADC channel 6
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#define ADCCH_PB7 7 //SARADC channel 7
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#define ADCCH_PF1 8 //SARADC channel 8
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#define ADCCH_PF2 9 //SARADC channel 9
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#define ADCCH_PF3 10 //SARADC channel 10
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#define ADCCH_PE6 11 //SARADC channel 11
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#define ADCCH_PE7 12 //SARADC channel 12
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#define ADCCH_WKO 13 //SARADC channel 13
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#define ADCCH_VBAT 14 //SARADC channel 14
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#define ADCCH_VRTC 15 //SARADC channel 15
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#define ADCCH_BGOP 15 //SARADC channel 15
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#define ADCCH_VUSB 15 //SARADC channel 15
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#define ADCCH_VTS 15 //SARADC channel 15
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#define ADCCH_MIC 15 //SARADC channel 15
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/*****************************************************************************
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* Module : Timer3 Capture Mapping选择列表
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* FUNCMCON2[7:4], 例如FUNCMCON2 = TMR3MAP_PA5;
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*****************************************************************************/
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#define TMR3MAP_PA5 (1 << 4) //G1 capture mapping: PA5
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#define TMR3MAP_PA6 (2 << 4) //G2 capture mapping: PA6
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#define TMR3MAP_PB0 (3 << 4) //G3 capture mapping: PB0
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#define TMR3MAP_PB1 (4 << 4) //G4 capture mapping: PB1
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#define TMR3MAP_PE0 (5 << 4) //G5 capture mapping: PE0
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#define TMR3MAP_PE3 (6 << 4) //G6 capture mapping: PE3
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#define TMR3MAP_PE4 (7 << 4) //G7 capture mapping: PE4
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#define TMR3MAP_PE5 (8 << 4) //G8 capture mapping: PE5
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#define TMR3MAP_PF2 (9 << 4) //G9 capture mapping: PF2
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/*****************************************************************************
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* Module : IRRX Mapping选择列表
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* FUNCMCON2[23:20], 例如FUNCMCON2 = IRMAP_PA5;
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*****************************************************************************/
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#define IRMAP_PA5 (1 << 20) //G1 capture mapping: PA5
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#define IRMAP_PA6 (2 << 20) //G2 capture mapping: PA6
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#define IRMAP_PB0 (3 << 20) //G3 capture mapping: PB0
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#define IRMAP_PB1 (4 << 20) //G4 capture mapping: PB1
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#define IRMAP_PE0 (5 << 20) //G5 capture mapping: PE0
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#define IRMAP_PE3 (6 << 20) //G6 capture mapping: PE3
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#define IRMAP_PE4 (7 << 20) //G7 capture mapping: PE4
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#define IRMAP_PE5 (8 << 20) //G8 capture mapping: PE5
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#define IRMAP_PF2 (9 << 20) //G9 capture mapping: PF2
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/*****************************************************************************
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* Module : Timer5 PWM Mapping选择列表
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* PWM0 = FUNCMCON1[11:8], PWM1 = FUNCMCON1[15:12], PWM2 = FUNCMCON1[19:16]
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* PWM3 = FUNCMCON1[23:20], PWM4 = FUNCMCON1[27:24], PWM5 = FUNCMCON1[31:28]
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* 示例：FUNCMCON1 = PWM0MAP_PA0;
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*****************************************************************************/
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#define PWM0MAP_PA0 (1 << 8) //G1 PWM0 mapping: PA0
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#define PWM1MAP_PA1 (1 << 12) //G1 PWM1 mapping: PA1
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#define PWM2MAP_PA2 (1 << 16) //G1 PWM2 mapping: PA2
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#define PWM3MAP_PA3 (1 << 20) //G1 PWM3 mapping: PA3
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#define PWM4MAP_PA4 (1 << 24) //G1 PWM3 mapping: PA4
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#define PWM5MAP_PA5 (1 << 28) //G1 PWM3 mapping: PA5
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#define PWM0MAP_PA6 (2 << 8) //G2 PWM0 mapping: PA6
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#define PWM1MAP_PA7 (2 << 12) //G2 PWM1 mapping: PA7
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#define PWM2MAP_PB0 (2 << 16) //G2 PWM2 mapping: PB0
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#define PWM3MAP_PB1 (2 << 20) //G2 PWM3 mapping: PB1
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#define PWM4MAP_PB2 (2 << 24) //G2 PWM3 mapping: PB2
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#define PWM5MAP_PB3 (2 << 28) //G2 PWM3 mapping: PB3
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#define PWM0MAP_PB4 (3 << 8) //G3 PWM0 mapping: PB4
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#define PWM1MAP_PB5 (3 << 12) //G3 PWM1 mapping: PB5
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#define PWM2MAP_PB6 (3 << 16) //G3 PWM2 mapping: PB6
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#define PWM3MAP_PB7 (3 << 20) //G3 PWM3 mapping: PB7
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#define PWM4MAP_PE6 (3 << 24) //G3 PWM3 mapping: PE6
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#define PWM5MAP_PE7 (3 << 28) //G3 PWM3 mapping: PE7
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#define PWM0MAP_PE0 (4 << 8) //G4 PWM0 mapping: PE0
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#define PWM1MAP_PE1 (4 << 12) //G4 PWM1 mapping: PE1
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#define PWM2MAP_PE2 (4 << 16) //G4 PWM2 mapping: PE2
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#define PWM3MAP_PE3 (4 << 20) //G4 PWM3 mapping: PE3
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#define PWM4MAP_PE4 (4 << 24) //G4 PWM3 mapping: PE4
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#define PWM5MAP_PE5 (4 << 28) //G4 PWM3 mapping: PE5
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#define PWM0MAP_PF0 (5 << 8) //G5 PWM0 mapping: PF0
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#define PWM1MAP_PF1 (5 << 12) //G5 PWM1 mapping: PF1
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#define PWM2MAP_PF2 (5 << 16) //G5 PWM2 mapping: PF2
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#define PWM3MAP_PF3 (5 << 20) //G5 PWM3 mapping: PF3
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#define PWM4MAP_PF4 (5 << 24) //G5 PWM3 mapping: PF4
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#define PWM5MAP_PF5 (5 << 28) //G5 PWM3 mapping: PF5
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/*****************************************************************************
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* Module : Clock output Mapping选择列表
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* FUNCMCON1[3:0], 例如FUNCMCON1 = CLKOMAP_PB3;
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*****************************************************************************/
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#define CLKOMAP_PB3 (1 << 0) //G1 Clock output mapping: PB3
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#define CLKOMAP_PB4 (2 << 0) //G2 Clock output mapping: PB4
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#define CLKOMAP_PE0 (3 << 0) //G3 Clock output mapping: PE0
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#define CLKOMAP_PF0 (4 << 0) //G4 Clock output mapping: PF0
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#define CLKOMAP_PF4 (5 << 0) //G5 Clock output mapping: PF4
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#define CLKOMAP_PE7 (6 << 0) //G6 Clock output mapping: PE7
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#define CLKOMAP_PA7 (7 << 0) //G7 Clock output mapping: PA7
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/*****************************************************************************
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* Module : sd0 Mapping选择列表
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* FUNCMCON0[3:0], 例如FUNCMCON0 = SD0MAP_G1;
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*****************************************************************************/
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#define SD0MAP_G1 (1 << 0) //G1 SDCLK(PB0), SDCMD(PB1), SDDAT0(PB2)
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#define SD0MAP_G2 (2 << 0) //G2 SDCLK(PB7), SDCMD(PB6), SDDAT0(PB5)
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#define SD0MAP_G3 (3 << 0) //G3 SDCLK(PE3), SDCMD(PE2), SDDAT0(PE1)
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/*****************************************************************************
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* Module : spi1 Mapping选择列表
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* FUNCMCON1[7:4], 例如FUNCMCON1 = SPI1MAP_G1;
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*****************************************************************************/
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#define SPI1MAP_G1 (1 << 4) //G1 SPI1CLK(PA1), SPI1DI(PA3), SPI1DO(PA0)
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#define SPI1MAP_G2 (2 << 4) //G2 SPI1CLK(PB1), SPI1DI(PB0), SPI1DO(PB2)
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#define SPI1MAP_G3 (3 << 4) //G3 SPI1CLK(PB7), SPI1DI(PB6), SPI1DO(PB5)
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#define SPI1MAP_G4 (4 << 4) //G4 SPI1CLK(PE6), SPI1DI(PE5), SPI1DO(PE4)
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#define SPI1MAP_G5 (5 << 4) //G5 SPI1CLK(PF3), SPI1DI(PF2), SPI1DO(PF1), SPI1DIOD2(PE1), SPI1DIOD3(PE2)
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#define SPI1MAP_G6 (6 << 4) //G6 SPI1CLK(PA4), SPI1DI(PA3), SPI1DO(PA2), SPI1DIOD2(PA1), SPI1DIOD3(PA0)
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/*****************************************************************************
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* Module : uart0 Mapping选择列表
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*****************************************************************************/
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#define UTX0MAP_PB3 (1 << 8) //G1 uart0 tx: PB3
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#define UTX0MAP_PA1 (2 << 8) //G2 uart0 tx: PA1
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#define UTX0MAP_PA3 (3 << 8) //G3 uart0 tx: PA3
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#define UTX0MAP_PE3 (4 << 8) //G4 uart0 tx: PE3
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#define UTX0MAP_PE5 (5 << 8) //G5 uart0 tx: PE5
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#define UTX0MAP_PE7 (6 << 8) //G6 uart0 tx: PE7
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#define UTX0MAP_PF5 (7 << 8) //G7 uart0 tx: PF5
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#define UTX0MAP_VUSB (8 << 8) //G8 uart0 tx: VUSB
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#define URX0MAP_PB4 (1 << 12) //G1 uart0 rx: PB4
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#define URX0MAP_PA0 (2 << 12) //G2 uart0 rx: PA0
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#define URX0MAP_PA2 (3 << 12) //G3 uart0 rx: PA2
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#define URX0MAP_PE2 (4 << 12) //G4 uart0 rx: PE2
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#define URX0MAP_PE4 (5 << 12) //G5 uart0 rx: PE4
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#define URX0MAP_PE6 (6 << 12) //G6 uart0 rx: PE6
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#define URX0MAP_TX (7 << 12) //uart0 map to TX pin by UT0TXMAP select(1线模式)
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#define URX0MAP_VUSB (8 << 12) //G8 uart0 rx: VUSB
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/*****************************************************************************
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* Module : Quadrate Decode Mapping选择列表
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* FUNCMCON2[19:16], 例如FUNCMCON2 = QDEC_MAP_G1;
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*****************************************************************************/
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#define QDEC_MAP_G1 (1 << 16) //G1 QDEC_A: PB0, QDEC_B: PB1
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#define QDEC_MAP_G2 (2 << 16) //G2 QDEC_A: PE1, QDEC_B: PE2
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#define QDEC_MAP_G3 (3 << 16) //G3 QDEC_A: PE6, QDEC_B: PE7
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/*****************************************************************************
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* Module : 录音文件类型列表
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*****************************************************************************/
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#define REC_NO 0
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#define REC_WAV 1 //PCM WAV
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#define REC_ADPCM 2 //ADPCM WAV
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#define REC_MP3 3
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#define REC_SBC 4
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/*****************************************************************************
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* Module : DAC SELECT
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*****************************************************************************/
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#define DAC_DIFF_MONO 0 //DAC差分单声道输出
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#define DAC_SINGLE_MONO 1 //DAC单端单声道输出
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/*****************************************************************************
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* Module : DAC OUT Sample Rate
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*****************************************************************************/
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#define DAC_OUT_44K1 0 //dac out sample rate 44.1K
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#define DAC_OUT_48K 1 //dac out sample rate 48K
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/*****************************************************************************
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* Module : DAC LDOH Select
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*****************************************************************************/
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#define AU_LDOH_2V4 0 //VDDAUD LDO voltage 2.4V
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#define AU_LDOH_2V5 1 //VDDAUD LDO voltage 2.5V
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#define AU_LDOH_2V7 2 //VDDAUD LDO voltage 2.7V
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#define AU_LDOH_2V9 3 //VDDAUD LDO voltage 2.9V
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#define AU_LDOH_3V1 4 //VDDAUD LDO voltage 3.1V
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#define AU_LDOH_3V2 5 //VDDAUD LDO voltage 3.2V
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/*****************************************************************************
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* Module : AUX or MIC Left&Right channel list
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* AUX: 可以任意左与右搭配，或只选择左，或只选择右
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*****************************************************************************/
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#define CH_MIC_PF0 0x0c //MIC(PF0) -> left mic -> sdadc left channel
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/*****************************************************************************
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* Module : 电池低电电压列表
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*****************************************************************************/
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#define VBAT_2V8 0 //2.8v
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#define VBAT_2V9 1 //2.9v
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#define VBAT_3V0 2 //3.0v
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||
#define VBAT_3V1 3 //3.1v
|
||
#define VBAT_3V2 4 //3.2v
|
||
#define VBAT_3V3 5 //3.3v
|
||
#define VBAT_3V4 6 //3.4v
|
||
#define VBAT_3V5 7 //3.5v
|
||
#define VBAT_3V6 8 //3.6v
|
||
#define VBAT_3V7 9 //3.7v
|
||
#define VBAT_3V8 10 //3.8v
|
||
|
||
/*****************************************************************************
|
||
* Module : uart0 printf IO列表
|
||
*****************************************************************************/
|
||
#define PRINTF_NONE 0 //关闭UART0打印信息
|
||
#define PRINTF_PB3 1
|
||
#define PRINTF_PA1 2
|
||
#define PRINTF_PA3 3
|
||
#define PRINTF_PE3 4
|
||
#define PRINTF_PE5 5
|
||
#define PRINTF_PE7 6
|
||
#define PRINTF_PF5 7
|
||
#define PRINTF_VUSB 8
|
||
/*****************************************************************************
|
||
* Module : GPIO list
|
||
*****************************************************************************/
|
||
#define IO_NONE 0
|
||
#define IO_PA0 1
|
||
#define IO_PA1 2
|
||
#define IO_PA2 3
|
||
#define IO_PA3 4
|
||
#define IO_PA4 5
|
||
#define IO_PA5 6
|
||
#define IO_PA6 7
|
||
#define IO_PA7 8
|
||
#define IO_PB0 9
|
||
#define IO_PB1 10
|
||
#define IO_PB2 11
|
||
#define IO_PB3 12
|
||
#define IO_PB4 13
|
||
#define IO_PB5 14
|
||
#define IO_PB6 15
|
||
#define IO_PB7 16
|
||
#define IO_PE0 17
|
||
#define IO_PE1 18
|
||
#define IO_PE2 19
|
||
#define IO_PE3 20
|
||
#define IO_PE4 21
|
||
#define IO_PE5 22
|
||
#define IO_PE6 23
|
||
#define IO_PE7 24
|
||
#define IO_PF0 25
|
||
#define IO_PF1 26
|
||
#define IO_PF2 27
|
||
#define IO_PF3 28
|
||
#define IO_PF4 29
|
||
#define IO_PF5 30
|
||
#define IO_MAX_NUM 30
|
||
|
||
#define IO_MUX_SDCLK 31
|
||
#define IO_MUX_SDCMD 32
|
||
|
||
#define IO_EDGE_FALL 0xfe
|
||
#define IO_EDGE_RISE 0xff
|
||
|
||
|
||
|
||
/*****************************************************************************
|
||
* Module : APP protocol
|
||
*****************************************************************************/
|
||
#define USE_NULL_APP 0
|
||
#define USE_AB_APP 1 //bluefit app
|
||
|
||
#endif //CONFIG_DEFINE_H
|