385 lines
10 KiB
C
385 lines
10 KiB
C
/*
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* Copyright (c) CompanyNameMagicTag 2021-2021. All rights reserved.
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* Description: Application Core Main function for Standard.
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* Author:
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* Create: 2021-03-09
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*/
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#include "main.h"
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#include "cmsis_os2.h"
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#include "ipc.h"
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#include "string.h"
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#include "rtc.h"
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#include "app_os_init.h"
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#include "gpio.h"
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#include "chip_io.h"
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#include "panic.h"
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#include "securec.h"
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#include "pinctrl_porting.h"
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#include "pinctrl.h"
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#include "tcxo.h"
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#include "systick.h"
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#include "cpu_trace.h"
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#include "application_version.h"
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#include "pmu.h"
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#include "pm_control.h"
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#include "watchdog.h"
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#include "watchdog_porting.h"
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#include "flash.h"
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#include "otp.h"
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#include "cpu_utils.h"
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#include "exception.h"
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#include "log_oml_exception.h"
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#include "uart.h"
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#include "uart_porting.h"
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#include "pmp_config.h"
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#include "hal_xip.h"
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#include "partition.h"
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#include "identity.h"
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#include "soc_osal.h"
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#include "arch_encoding.h"
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#include "arch_port.h"
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#include "flash_porting.h"
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#include "clocks_switch.h"
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#include "pm_clocks.h"
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#include "pmu_pg.h"
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#include "efuse.h"
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#if defined(__LITEOS__)
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#include "los_task_pri.h"
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#include "los_printf_pri.h"
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#elif defined(__FREERTOS__)
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#include "FreeRTOS.h"
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#include "task.h"
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#include "cache.h"
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#if defined(XLTCFG_SUPPORT_MEMMNG)
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#include "xlt_memory.h"
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#endif
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#endif
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#define WDT_TIMEOUT_S 30
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#define IMG_NUM_MAX 2
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#define IMG_SEC 0
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#define IMG_HIFI 1
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#define SW_PRINT_DELAY 200ULL
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#define CSR_WST_VAL 0x4
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#define CSR_WST_POS 0xb
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#define XIP_CACHE_INTR_MASK 0xa3006128
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#define XIP_CACHE_WRITE_DATA_DELAY_INTR_MASK 0x8
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#define XIP_CACHE_ENABLE_WRITE_INTR_MASK 0x1
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extern uint32_t __l2m_gpu_text_start;
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extern uint32_t __l2m_gpu_text_load;
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extern uint32_t __l2m_gpu_text_end;
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extern uint32_t __l2m_gpu_bss_start;
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extern uint32_t __l2m_gpu_bss_end;
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extern uint32_t __l2m_gpu_data_start;
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extern uint32_t __l2m_gpu_data_load;
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extern uint32_t __l2m_gpu_data_end;
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#ifndef CONFIG_PSRAM_SUPPORT
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extern uint32_t __l2m_dsp_text_start;
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extern uint32_t __l2m_dsp_text_load;
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extern uint32_t __l2m_dsp_text_end;
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extern uint32_t __l2m_dsp_bss_start;
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extern uint32_t __l2m_dsp_bss_end;
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extern uint32_t __l2m_dsp_data_start;
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extern uint32_t __l2m_dsp_data_load;
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extern uint32_t __l2m_dsp_data_end;
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#endif
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extern char __heap_start;
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extern void *g_intheap_size;
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extern char __extend_heap_start;
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extern void *g_extend_heap_size;
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#if (defined SUPPORT_CXX)
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typedef void (*SystemInitFunc)(void);
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extern char __init_array_start;
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extern char __init_array_end;
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#if defined(__FREERTOS__)
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static void OsCacheInit(void);
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#else
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void OsCacheInit(void);
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#endif
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void OsSetMainTask(void);
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void *OsGetMainTask(void);
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static void system_init_array(uintptr_t start, uintptr_t end)
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{
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if (start >= end) {
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return;
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}
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SystemInitFunc func;
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uintptr_t *it = (uintptr_t *)start;
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for (; it != (uintptr_t *)end; ++it) {
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func = (SystemInitFunc)(*it);
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func();
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}
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}
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#endif
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#if defined(__FREERTOS__)
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static void OsCacheInit(void)
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{
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dsb();
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ArchICacheInvAll();
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ArchDCacheInvAll();
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dsb();
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(void)ArchICacheEnable(CACHE_32KB);
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(void)ArchICachePrefetchEnable(CACHE_PREF_1_LINES);
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(void)ArchDCacheEnable(CACHE_32KB);
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(void)ArchDCachePrefetchEnable(CACHE_PREF_1_LINES, CACHE_PREF_1_LINES);
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}
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#endif
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static void copy_from_flash_to_l2ram(void)
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{
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uint32_t size = (uint32_t)(&__l2m_gpu_text_end) - (uint32_t)(&__l2m_gpu_text_start);
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(void)memcpy_s((void *)((uint32_t)(&__l2m_gpu_text_start)), size, (void *)(uint32_t)(&__l2m_gpu_text_load), size);
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size = (uint32_t)(&__l2m_gpu_data_end) - (uint32_t)(&__l2m_gpu_data_start);
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(void)memcpy_s((void *)((uint32_t)(&__l2m_gpu_data_start)), size, (void *)(uint32_t)(&__l2m_gpu_data_load), size);
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size = (uint32_t)(&__l2m_gpu_bss_end) - (uint32_t)(&__l2m_gpu_bss_start);
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(void)memset_s((void *)((uint32_t)(&__l2m_gpu_bss_start)), size, 0, size);
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#ifndef CONFIG_PSRAM_SUPPORT
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#if DSP_L2RAM_AREA_SIZE < DSP_L2RAM_AREA_TOTAL
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size = (uint32_t)(&__l2m_dsp_text_end) - (uint32_t)(&__l2m_dsp_text_start);
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(void)memcpy_s((void *)((uint32_t)(&__l2m_dsp_text_start)), size, (void *)(uint32_t)(&__l2m_dsp_text_load), size);
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size = (uint32_t)(&__l2m_dsp_data_end) - (uint32_t)(&__l2m_dsp_data_start);
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(void)memcpy_s((void *)((uint32_t)(&__l2m_dsp_data_start)), size, (void *)(uint32_t)(&__l2m_dsp_data_load), size);
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size = (uint32_t)(&__l2m_dsp_bss_end) - (uint32_t)(&__l2m_dsp_bss_start);
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(void)memset_s((void *)((uint32_t)(&__l2m_dsp_bss_start)), size, 0, size);
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#endif
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#endif
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}
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static void service_init(void)
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{
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cpu_utils_init();
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hal_register_exception_dump_callback(log_exception_dump);
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uapi_partition_init();
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}
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static void pio_func_init(void)
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{
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size_t pin_num;
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hal_pio_config_t *pio_func = NULL;
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get_pio_func_config(&pin_num, &pio_func);
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for (pin_t i = S_EGPIO0; i < pin_num; i++) {
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if (pio_func[i].func != HAL_PIO_FUNC_INVALID) {
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if (pio_func[i].func == HAL_PIO_FUNC_DEFAULT_HIGH_Z) {
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uapi_pin_set_mode(i, (pin_mode_t)HAL_PIO_FUNC_GPIO);
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uapi_gpio_set_dir(i, GPIO_DIRECTION_INPUT);
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} else {
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uapi_pin_set_mode(i, (pin_mode_t)pio_func[i].func);
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uapi_pin_set_ds(i, (pin_drive_strength_t)pio_func[i].drive);
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}
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if (pio_func[i].pull != HAL_PIO_PULL_MAX) {
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uapi_pin_set_pull(i, (pin_pull_t)pio_func[i].pull);
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}
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if (pio_func[i].ie != HAL_PIO_IE_MAX) {
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uapi_pin_set_ie(i, (pin_input_enable_t)pio_func[i].ie);
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}
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}
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}
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}
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static void gpio_func_init(void)
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{
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size_t pin_num = 0;
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hal_gpio_config_t *gpio_func = NULL;
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get_gpio_func_config(&pin_num, &gpio_func);
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for (pin_t i = 0; i < pin_num; i++) {
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uapi_gpio_set_dir(gpio_func[i].gpio, (gpio_direction_t)gpio_func[i].direction);
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if (gpio_func[i].direction == HAL_GPIO_DIRECTION_INPUT && gpio_func[i].callback != NULL) {
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uapi_gpio_register_isr_func(gpio_func[i].gpio, gpio_func[i].triger, gpio_func[i].callback);
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}
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if (gpio_func[i].direction == HAL_GPIO_DIRECTION_OUTPUT) {
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uapi_gpio_set_val(gpio_func[i].gpio, (gpio_level_t)gpio_func[i].level);
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}
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}
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}
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static void board_init(uint32_t flash_id, uint32_t flash_unique_id)
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{
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/* flash init */
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flash_funcreg_adapt(0);
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flash_save_manufacturer(0, flash_id);
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uapi_flash_init(0);
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uapi_flash_config_cmd_at_xip_mode(0, (uint8_t)flash_unique_id);
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uapi_flash_switch_to_cache_mode(0);
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PRINT("Flash id is %x, init success"NEWLINE, flash_id);
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pio_func_init();
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gpio_func_init();
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}
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static void chip_xip_init(void)
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{
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hal_xip_init();
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hal_xip_config_interrupt_type(XIP_0, XIP_INTR_NMI);
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write_csr(0x7d0, read_csr(0x7d0) | (CSR_WST_VAL << CSR_WST_POS));
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// Mask interrupts caused by CACHE2AHBM module state machine timeout
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reg16_clrbit(XIP_CACHE_INTR_MASK, XIP_CACHE_WRITE_DATA_DELAY_INTR_MASK);
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reg16_clrbit(XIP_CACHE_INTR_MASK, XIP_CACHE_ENABLE_WRITE_INTR_MASK);
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}
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static void chip_enable_ulp_ram(void)
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{
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writew(0x5702c50c, 0x1);
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writew(0x5700450c, 0x1);
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}
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static void clocks_set_xip_div(void)
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{
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// xip cache div = 2
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writew(0xa3006014, 0x1); // sync mode = 1, high freq
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regw_clrbits(0xa3006000, 0x24, 0x0, 0x1); // close xip cache clk en
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regw_clrbits(0xa3006000, 0x24, 0x3, 0x1); // close xip cache div en
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regw_setbits(0xa3006000, 0x24, 0x4, 0x2, 0x2); // xip cache div = 2 from xip_opi
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regw_setbits(0xa3006000, 0x24, 0x3, 0x1, 0x1); // open xip cache div en
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regw_setbits(0xa3006000, 0x24, 0x0, 0x1, 0x1); // open xip cache clk en
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}
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static void chip_init(void)
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{
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chip_enable_ulp_ram();
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clocks_pll_init_vote();
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uapi_pin_init();
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uapi_gpio_init();
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uapi_efuse_init();
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/* uart init */
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uart_config_init();
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PRINT("App uart init succ."NEWLINE);
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uapi_tcxo_init();
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uapi_systick_init();
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chip_xip_init();
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#if TCXO_CLK_DYN_ADJUST == YES
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init_mcu_core_clk();
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#endif
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uapi_rtc_init();
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uapi_rtc_adapter(RTC_0, RTC_0_IRQN, g_aucIntPri[RTC_0_IRQN]);
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uapi_dma_init();
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uapi_dma_open();
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clocks_set_xip_div();
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uapi_clocks_init();
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uapi_pm_control(PM_SDIO_POWER_UP_AND_RUN);
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}
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static void liteos_kernel_init(void)
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{
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#ifdef __LITEOS__
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/* enable icache and dcahce */
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pmp_init();
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OsCacheInit();
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ArchSetExcHook((EXC_PROC_FUNC)do_fault_handler);
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ArchSetNMIHook((NMI_PROC_FUNC)do_hard_fault_handler);
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OsSetMainTask();
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OsCurrTaskSet(OsGetMainTask());
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(void)osKernelInitialize();
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#if defined SUPPORT_CXX
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system_init_array((uintptr_t)&__init_array_start, (uintptr_t)&__init_array_end);
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#endif
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#endif
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}
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static void freertos_kernel_init(void)
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{
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#ifdef __FREERTOS__
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/* os kernel adapt config */
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vPortHwiInit();
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/* enable icache and dcahce */
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pmp_init();
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OsCacheInit();
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/* memory pool init */
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#if defined(XLTCFG_SUPPORT_MEMMNG)
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g_heap = (void *)&__heap_start;
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if (xlt_mem_init(g_heap, (uint32_t)&g_intheap_size)) {
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panic(PANIC_MEMORY, __LINE__);
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}
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g_extend_heap = (void *)&__extend_heap_start;
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if (xlt_mem_init(g_extend_heap, (uint32_t)&g_extend_heap_size)) {
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panic(PANIC_MEMORY, __LINE__);
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}
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#endif
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osal_irq_request(NON_MASKABLE_INT_IRQN, (osal_irq_handler)do_fault_handler_freertos, NULL, NULL, NULL);
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osal_irq_enable(NON_MASKABLE_INT_IRQN);
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(void)osKernelInitialize();
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vTimerTickInit();
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#if defined SUPPORT_CXX
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system_init_array((uintptr_t)&__init_array_start, (uintptr_t)&__init_array_end);
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#endif
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#endif
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}
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static void chip_watchdog_init(void)
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{
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watchdog_turnon_clk();
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watchdog_func_adapt(CHIP_WDT_TIMEOUT_32S);
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uapi_watchdog_init(CHIP_WDT_TIMEOUT_32S);
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uapi_watchdog_enable(WDT_MODE_INTERRUPT);
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}
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static void kernel_init(void)
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{
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chip_watchdog_init();
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pmu1_dsp_l2ram_config(0);
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copy_from_flash_to_l2ram();
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panic_init();
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freertos_kernel_init();
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liteos_kernel_init();
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}
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static startup_table ssb_to_app_table;
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void sec_main(const void *startup_details_table)
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{
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if (memcpy_s(&ssb_to_app_table, sizeof(ssb_to_app_table), startup_details_table, sizeof(ssb_to_app_table)) != EOK) {
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panic(PANIC_MEMORY, __LINE__);
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return;
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}
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kernel_init();
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chip_init();
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board_init(ssb_to_app_table.ssb_to_application_flash_id, ssb_to_app_table.ssb_to_application_flash_unique_id);
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service_init();
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app_os_init(NULL, 0);
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(void)osKernelStart();
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for (;;) {
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}
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}
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