145 lines
5.3 KiB
C
145 lines
5.3 KiB
C
/*
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* Copyright (c) CompanyNameMagicTag 2018-2020. All rights reserved.
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* Description: Basic chip definitions
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* Author:
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* Create: 2018-10-15
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*/
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#ifndef LIB_COMMON_HEADERS_CHIP_DEFINITIONS_H
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#define LIB_COMMON_HEADERS_CHIP_DEFINITIONS_H
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/** @defgroup CHIP_Base CHIP Base Definitions
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* CHIP Base Definitions
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* @ingroup CHIP_Base
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* */
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/** @defgroup CHIP_ARMCORE CHIP ARM Core Specifics
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* CHIP ARM Core Application Core Specifics
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* @ingroup CHIP_Base
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* @{
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* */
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#define BT 0
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#define PROTOCOL 1
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#define APPS 2
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#define GNSS 3
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#define SECURITY 4
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#define HIFI PROTOCOL
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#define WIFI 5
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#define CONTROL_CORE 6
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#define CM3 0
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#define CM7 1
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#define RISCV31 2
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#define RISCV70 3
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#define CHIP_LIBRA (TARGET_CHIP_LIBRA)
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#define CHIP_SOCMN1 (TARGET_CHIP_SOCMN1)
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#define CHIP_BS25 (TARGET_CHIP_BS25)
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#define CHIP_BRANDY (TARGET_CHIP_BRANDY)
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#if (CHIP_LIBRA == 1)
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#define MASTER_BY_ALL APPS
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#define CORE_NUMS 5 // Total cores in chip
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#define CPU_NUM 3 // Total cpus in chip
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#elif (CHIP_SOCMN1 == 1)
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#define MASTER_BY_ALL APPS
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#define CORE_NUMS 4 // Total cores in chip
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#define CPU_NUM 3 // Total cpus in chip
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#elif (CHIP_BS25 == 1)
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#define MASTER_BY_ALL APPS
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#define CORE_NUMS 2 // Total cores in chip
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#define CPU_NUM 2 // Total cpus in chip
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#elif (CHIP_BS21 == 1)
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#define MASTER_BY_ALL APPS
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#define CORE_NUMS 1 // Total cores in chip
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#define CPU_NUM 1 // Total cpus in chip
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#elif (CHIP_WS53 == 1)
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#define MASTER_BY_ALL APPS
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#define CORE_NUMS 2 // Total cores in chip
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#define CPU_NUM 2 // Total cpus in chip
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#elif (CHIP_WS63 == 1)
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#define MASTER_BY_ALL APPS
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#define CORE_NUMS 1 // Total cores in chip
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#define CPU_NUM 1 // Total cpus in chip
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#elif (CHIP_BRANDY == 1)
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#define MASTER_BY_ALL APPS
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#define CORE_NUMS 3 // Total cores in chip
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#define CPU_NUM 3 // Total cpus in chip
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#else
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#error Please define master control core
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#endif
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#define OTHER_CPU_NUM (CPU_NUM - 1) // Other cpus number, exclude current cpu.
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#define MASTER_BY_LIBRA_ONLY (CHIP_LIBRA && (CORE == APPS))
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#define MASTER_BY_SOCMN1_ONLY (CHIP_SOCMN1 && (CORE == APPS))
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#define MASTER_BY_BS25_ONLY (CHIP_BS25 && (CORE == APPS))
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#define MASTER_BY_BS21_ONLY (CHIP_BS21 && (CORE == APPS))
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#define MASTER_BY_BRANDY_ONLY (CHIP_BRANDY && (CORE == APPS))
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#define MASTER_BY_WS53_ONLY (CHIP_WS53 && (CORE == APPS))
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#define MASTER_ONLY (MASTER_BY_LIBRA_ONLY || \
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MASTER_BY_SOCMN1_ONLY || MASTER_BY_BS25_ONLY || \
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MASTER_BY_BRANDY_ONLY || MASTER_BY_BS21_ONLY || \
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MASTER_BY_WS53_ONLY)
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#define MCU_ONLY (MASTER_BY_LIBRA_ONLY || MASTER_BY_SOCMN1_ONLY || \
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MASTER_BY_BS25_ONLY || MASTER_BY_BRANDY_ONLY || \
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MASTER_BY_WS53_ONLY || CHIP_WS63 || CHIP_BS21)
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#define SLAVE_BY_LIBRA_BT (CHIP_LIBRA && (CORE == BT))
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#define SLAVE_BY_LIBRA_GNSS (CHIP_LIBRA && (CORE == GNSS))
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#define SLAVE_BY_LIBRA_SECURITY (CHIP_LIBRA && (CORE == SECURITY))
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#define SLAVE_BY_LIBRA_ONLY (SLAVE_BY_LIBRA_BT || SLAVE_BY_LIBRA_GNSS || SLAVE_BY_LIBRA_SECURITY)
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#define SLAVE_BY_SOCMN1_ONLY (CHIP_SOCMN1 && (CORE == BT))
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#define SLAVE_BY_BS25_ONLY (CHIP_BS25 && (CORE == BT))
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#define SLAVE_BY_BRANDY_BT (CHIP_BRANDY && (CORE == BT))
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#define SLAVE_BY_BRANDY_DSP (CHIP_BRANDY && (CORE == DSP))
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#define SLAVE_BY_BRANDY_ONLY (SLAVE_BY_BRANDY_BT || SLAVE_BY_BRANDY_DSP)
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#define SLAVE_BY_WS53_ONLY (CHIP_WS53 && (CORE == CONTROL_CORE))
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#define CHIP_LIBRA_FPGA (CHIP_LIBRA && (LIBRA_CHIP_FPGA))
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#define CHIP_LIBRA_CS (CHIP_LIBRA && (LIBRA_CHIP_CS))
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#define CHIP_SOCMN1_FPGA (CHIP_SOCMN1 && (SOCMN1_CHIP_FPGA))
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#define CHIP_SOCMN1_V100 (CHIP_SOCMN1 && (SOCMN1_CHIP_V100))
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#define CHIP_SOCMN1_V200 (CHIP_SOCMN1 && (SOCMN1_CHIP_V200))
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#define CHIP_BS25_FPGA (CHIP_BS25 && (BS25_CHIP_FPGA))
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#define CHIP_BS25_V100 (CHIP_BS25 && (BS25_CHIP_V100))
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#ifdef PRE_FPGA
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#define FPGA 1
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#define ASIC 0
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#endif
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#ifdef PRE_ASIC
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#define FPGA 0
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#define ASIC 1
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#endif
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#define CHIP_BS21_FPGA (CHIP_BS21 && (FPGA))
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#define CHIP_BS21_V100 (CHIP_BS21 && (ASIC))
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#define CHIP_WS63_FPGA (CHIP_WS63 && (FPGA))
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#define CHIP_WS63_V100 (CHIP_WS63 && (ASIC))
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#define CHIP_BRANDY_FPGA (CHIP_BRANDY && (BRANDY_CHIP_FPGA))
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#define CHIP_BRANDY_V100 (CHIP_BRANDY && (BRANDY_CHIP_V100))
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#define CHIP_WS53_FPGA (CHIP_WS53 && (FPGA))
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#define CHIP_FPGA (CHIP_LIBRA_FPGA || CHIP_SOCMN1_FPGA || CHIP_BS25_FPGA || \
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CHIP_BRANDY_FPGA || CHIP_BS21_FPGA || CHIP_WS63_FPGA || CHIP_WS53_FPGA)
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#define CHIP_SOCMN1_ASIC (CHIP_SOCMN1_V100 || CHIP_SOCMN1_V200)
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#define CHIP_BS25_ASIC (CHIP_BS25_V100)
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#define CHIP_BS21_ASIC (CHIP_BS21_V100)
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#define CHIP_BRANDY_ASIC (CHIP_BRANDY_V100)
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#define CHIP_WS63_ASIC (CHIP_WS63_V100)
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#define CHIP_ASIC (CHIP_LIBRA_CS || CHIP_SOCMN1_ASIC || \
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CHIP_BS25_ASIC || CHIP_BRANDY_ASIC || \
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CHIP_BS21_ASIC || CHIP_WS63_ASIC)
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/** @} end of group CHIP_ARMCORE */
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#endif
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