66 lines
2.8 KiB
C
66 lines
2.8 KiB
C
/*
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* Copyright (c) CompanyNameMagicTag 2020-2021. All rights reserved.
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* Description: header file for es8311 driver
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*/
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#ifndef ES8311_PRIV_H
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#define ES8311_PRIV_H
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#include "td_type.h"
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/*
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* ES8311_REGISTER NAME_REG_REGISTER ADDR
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*/
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#define ES8311_RESET_REG00 0x00 /* reset digital,csm,clock manager etc. */
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/*
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* Clock Scheme Register definition
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*/
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#define ES8311_CLK_MANAGER_REG01 0x01 /* select clk src for mclk, enable clock for codec */
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#define ES8311_CLK_MANAGER_REG02 0x02 /* clk divider and clk multiplier */
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#define ES8311_CLK_MANAGER_REG03 0x03 /* adc fsmode and osr */
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#define ES8311_CLK_MANAGER_REG04 0x04 /* dac osr */
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#define ES8311_CLK_MANAGER_REG05 0x05 /* clk divier for adc and dac */
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#define ES8311_CLK_MANAGER_REG06 0x06 /* bclk inverter and divider */
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#define ES8311_CLK_MANAGER_REG07 0x07 /* tri-state, lrck divider */
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#define ES8311_CLK_MANAGER_REG08 0x08 /* lrck divider */
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#define ES8311_SDPIN_REG09 0x09 /* dac serial digital port */
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#define ES8311_SDPOUT_REG0A 0x0A /* adc serial digital port */
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#define ES8311_SYSTEM_REG0B 0x0B /* system */
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#define ES8311_SYSTEM_REG0C 0x0C /* system */
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#define ES8311_SYSTEM_REG0D 0x0D /* system, power up/down */
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#define ES8311_SYSTEM_REG0E 0x0E /* system, power up/down */
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#define ES8311_SYSTEM_REG0F 0x0F /* system, low power */
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#define ES8311_SYSTEM_REG10 0x10 /* system */
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#define ES8311_SYSTEM_REG11 0x11 /* system */
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#define ES8311_SYSTEM_REG12 0x12 /* system, Enable DAC */
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#define ES8311_SYSTEM_REG13 0x13 /* system */
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#define ES8311_SYSTEM_REG14 0x14 /* system, select DMIC, select analog pga gain */
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#define ES8311_ADC_REG15 0x15 /* ADC, adc ramp rate, dmic sense */
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#define ES8311_ADC_REG16 0x16 /* ADC */
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#define ES8311_ADC_REG17 0x17 /* ADC, volume */
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#define ES8311_ADC_REG18 0x18 /* ADC, alc enable and winsize */
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#define ES8311_ADC_REG19 0x19 /* ADC, alc maxlevel */
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#define ES8311_ADC_REG1A 0x1A /* ADC, alc automute */
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#define ES8311_ADC_REG1B 0x1B /* ADC, alc automute, adc hpf s1 */
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#define ES8311_ADC_REG1C 0x1C /* ADC, equalizer, hpf s2 */
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#define ES8311_DAC_REG31 0x31 /* DAC, mute */
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#define ES8311_DAC_REG32 0x32 /* DAC, volume */
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#define ES8311_DAC_REG33 0x33 /* DAC, offset */
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#define ES8311_DAC_REG34 0x34 /* DAC, drc enable, drc winsize */
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#define ES8311_DAC_REG35 0x35 /* DAC, drc maxlevel, minilevel */
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#define ES8311_DAC_REG37 0x37 /* DAC, ramprate */
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#define ES8311_GPIO_REG44 0x44 /* GPIO, dac2adc for test */
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#define ES8311_GP_REG45 0x45 /* GP CONTROL */
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#define ES8311_CHD1_REGFD 0xFD /* CHIP ID1 */
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#define ES8311_CHD2_REGFE 0xFE /* CHIP ID2 */
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#define ES8311_CHVER_REGFF 0xFF /* VERSION */
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#define ES8311_MAX_REGISTER 0xFF
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#define ES8311_PDN_DAC_BIT (1 << 1)
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#define ES8311_CHIP_ID 0x21D
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#endif
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