116 lines
3.3 KiB
C
116 lines
3.3 KiB
C
/*
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* Copyright (c) CompanyNameMagicTag 2021-2022. All rights reserved.
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*/
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#ifndef _ARCH_CACHE_H
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#define _ARCH_CACHE_H
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#include "stdint.h"
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typedef enum {
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CACHE_4KB = 0,
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CACHE_8KB = 2,
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CACHE_16KB = 4,
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CACHE_32KB = 6,
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} CacheSize;
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typedef enum {
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CACHE_PREF_1_LINES = 0,
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CACHE_PREF_2_LINES = 1,
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CACHE_PREF_3_LINES = 2,
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CACHE_PREF_4_LINES = 3,
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CACHE_PREF_5_LINES = 4,
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CACHE_PREF_6_LINES = 5,
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CACHE_PREF_7_LINES = 6,
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CACHE_PREF_8_LINES = 7,
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} CachePrefLines;
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/* riscv cache register config */
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/*
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* csr_bit[0] ICEN Instruction cache is enabled when this bit is set to 1b1. Default is disabled.
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* Bit[2:1] ICS Instruction cache size: 2b00=4KB, 2b01=8KB, 2b10=16KB, 2b11=32KB. Default is 32KB
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*/
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#define ICCTL 0x7C0
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#define ICCTL_ENABLE 0x1
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/*
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* Bit[0] DCEN Data cache is enabled when this bit is set to 1b1. Default is disabled.
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* Bit[2:1] DCS Data cache size: 2b00=4KB, 2b01=8KB, 2b10=16KB, 2b11=32KB. Default is 32KB
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*/
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#define DCCTL 0x7C1
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#define DCCTL_ENABLE 0x1
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/*
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* Bit[0] VA Instruction cache invalidation by all or VA: 1b0=all, 1b1=VA.
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* Bit[2] ICIV Initiate instruction cache invalidation when this bit is set to 1b1.
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When the instruction cache invalidation is by VA, the virtual address is specified in icinva CSR
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*/
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#define ICMAINT 0x7C2
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#define DCMAINT 0x7C3
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#define ICINCVA 0x7C4
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#define DCINCVA 0x7C5
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#define VA 0x1
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#define ICIV (0x1U << 2)
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#define DCIV (0x1U << 2)
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#define DCC (0x1U << 3)
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#define ICACHE_BY_ALL ICIV
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#define ICACHE_BY_VA (ICIV | VA)
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#define DCACHE_INV_BY_VA (DCIV | VA)
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#define DCACHE_CLEAN_ALL DCC
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#define DCACHE_CLEAN_BY_VA (DCC | VA)
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#define DCACHE_FLUSH_BY_VA (DCC | DCIV | VA)
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#define DCACHE_FLUSH_ALL (DCC | DCIV)
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#define APREFI 0x7C6
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#define APREFD 0x7C7
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#define IAPEN 0x1
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#define SAPEN (0x1U << 4)
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#define CACHE_LINE_SIZE 32
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uint32_t ArchICacheEnable(CacheSize icclSize);
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uint32_t ArchDCacheEnable(CacheSize dcclSize);
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uint32_t ArchICachePrefetchEnable(CachePrefLines iclValue);
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uint32_t ArchDCachePrefetchEnable(CachePrefLines iclValue, CachePrefLines sclValue);
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void ArchDCacheFlushByVa(uintptr_t baseAddr, uint32_t size);
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void ArchICacheFlushByVa(uintptr_t baseAddr, uint32_t size);
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void ArchDCacheInvByVa(uintptr_t baseAddr, uint32_t size);
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void ArchDCacheCleanByVa(uintptr_t baseAddr, uint32_t size);
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void ArchICacheFlushByAddr(uintptr_t startAddr, uintptr_t endAddr);
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void ArchDCacheFlushByAddr(uintptr_t startAddr, uintptr_t endAddr);
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void ArchDCacheCleanByAddr(uintptr_t startAddr, uintptr_t endAddr);
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void ArchDCacheInvByAddr(uintptr_t startAddr, uintptr_t endAddr);
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void ArchICacheFlush(void);
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void ArchDCacheFlush(void);
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void ArchDCacheClean(void);
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static inline uintptr_t ArchCacheAlign(uintptr_t addr, uint32_t boundary)
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{
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return (addr + boundary - 1) & ~((uintptr_t)(boundary - 1));
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}
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#ifndef ALIGN
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#define ALIGN(addr, boundary) ArchCacheAlign(addr, boundary)
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#endif
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#define flush_dcache(start, end) ArchDCacheFlushByAddr(start, end)
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#define flush_icache() ArchICacheFlush()
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#endif /* _ARCH_CACHE_H */
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