76 lines
3.0 KiB
C
76 lines
3.0 KiB
C
/*----------------------------------------------------------------------------
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* Copyright (c) CompanyNameMagicTag 2021. All rights reserved.
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* All rights reserved.
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice, this list of
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* conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice, this list
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* of conditions and the following disclaimer in the documentation and/or other materials
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* provided with the distribution.
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* 3. Neither the name of the copyright holder nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific prior written
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* permission.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*---------------------------------------------------------------------------*/
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#ifndef DPAL_REG_CONFIG_H
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#define DPAL_REG_CONFIG_H
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#ifdef __cplusplus
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#if __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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#endif /* __cplusplus */
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#define MMC_REG_BASE 0x70021000
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#define MMC_CLK_REG_BASE 0x5000A000
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#define MMC_CMU_CLK (MMC_CLK_REG_BASE + 0x0042C)
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#define MMC_CMU_CLK_INIT 0x0
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#define MMC_CMU_CLK_RDWR 0x1
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#define MMC_CMU_CLK_MASK 0x7
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#define EMMC_FREQ_MASK 0x7
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#define EMMC_FREQ_SHIFT 0
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#define FMC_REG_BASE 0x70022000
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#define FMC_MEM_BASE 0x38000000
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#define DPAL_CRG_REG_BASE 0x70001000
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#ifndef MMC_CRG_REG_BASE
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#define MMC_CRG_REG_BASE (DPAL_CRG_REG_BASE + 0x0150)
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#endif
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#define IORESOURCE_IO 0x00000100 /* PCI/ISA I/O ports */
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#define IORESOURCE_MEM 0x00000200
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#define IORESOURCE_REG 0x00000300 /* Register offsets */
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#define IORESOURCE_IRQ 0x00000400
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#define IORESOURCE_DMA 0x00000800
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#define IORESOURCE_BUS 0x00001000
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#define OS_RISCV_SYS_VECTOR_CNT 26
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#ifdef EMMC_BOOT
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#define NUM_HAL_INTERRUPT_EMMC (21 + OS_RISCV_SYS_VECTOR_CNT)
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#else
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#define NUM_HAL_INTERRUPT_EMMC (15 + OS_RISCV_SYS_VECTOR_CNT)
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#define NUM_HAL_INTERRUPT_SDIO (18 + OS_RISCV_SYS_VECTOR_CNT)
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#endif
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#ifdef __cplusplus
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#if __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* __cplusplus */
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#endif /* DPAL_REG_CONFIG_H */
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